This invention relates generally to data processing systems and is particularly directed to the prevention of loss of data stored in a nonvolatile memory in a data processing system arising from variations in an input voltage provided thereto.
Programmable memories are increasingly being utilized for various applications ranging from the timed control of a device by means of user initiated inputs to the temporary storage and processing of data in a computer terminal. These programmable memories may assume various forms such as random access memory (RAM) or an electrically alterable read only memory (EEROM or EAROM) depending upon the specific application in which the integrated circuit (IC) memory is utilized. In the RAM type of programmable memory, the data stored therein is lost when power is removed from the memory, this giving rise to the term "volatile" in describing this type of memory. The EEROM type of memory is nonvolatile and thus maintains the data stored therein following the removal of power therefrom. However, data is frequently erased or over-written in these nonvolatile memories as a result of input voltage variations giving rise to the generation of erroneous write commands by a system controller which are provided to the nonvolatile memory.
Various approaches have been undertaken in the prior art to reduce or eliminate the possibility of loss of data in a nonvolatile memory arising from input voltage transients. Some approaches make use of a second nonvolatile memory in the system which is coupled to the first nonvolatile memory and reads the contents therefrom in response to a reduction in the input voltage below a designated voltage level. The second nonvolatile memory is not responsive to a write command from the system controller and is thus not subject to erroneous over-writing of data by the controller into the nonvolatile memory. The requirement for a second nonvolatile memory in this approach precludes its use in those system where low cost and reduced complexity are primary considerations.
Other approaches have used various input voltage detection circuit arrangements for disabling the memory when the input voltage drops below a predetermined threshold voltage. One example of this approach can be found in U.S. Pat. No. 4,493,000 to Edwards wherein a Zener diode responsive to the power supply voltage controls the voltage level at which a transistor turns on, with the transistor enabling a logic device in which data is stored or processed. The Zener diode in this approach is not only expensive but also exhibits a characteristic wide operating tolerance at the low voltages used in a data processing system. Another approach is disclosed in U.S. Pat. No. 4,485,456 to Toyoda wherein various signals within a data processing system are monitored in generating, when the main power voltage drops lower than a reference voltage, an operation/halt signal which, in turn, results in the providing of a write inhibit signal by setting a D-type latch at the timing of the transition of the next instruction fetch (NIF) signal to the active mode and providing the write inhibit signal to a read/write memory. Another approach maintains the output-enable pin of the nonvolatile memory inactive until the input power reaches a selected voltage level. These approaches require the processing of various digital signals in the data processing system and thus involve various logic gates and signal timing considerations.
Still another approach to a write protect circuit in a data processing system having a nonvolatile memory monitors the voltage at the input to a voltage regulator which provides various DC outputs for energizing system logic circuitry. When the voltage at the input of the voltage regulator drops below a predetermined level, the nonvolatile memory is automatically deselected. An example of this approach can be found in Magnavox Service Manual No. 7362A, issued March, 1979. This approach suffers from the limitation that the reduction in input voltage which must be sensed in order to inactivate the memory device to prevent the erroneous writing of data therein is small in comparison with the operating voltage thus requiring a detection circuit having a relatively high voltage discrimination capability and comprised of components having high accuracy, e.g., 2% tolerance.
The present invention represents an improvement over prior art memory loss protection circuits by providing for the comparison of an input voltage drop which initiates deselection of nonvolatile memory device with a minimum operating voltage. By thus comparing a reduction in input voltage to a low operating voltage level, the voltage discrimination characteristics of the memory loss protection circuit may be relaxed permitting the use of reduced component ratings and less demanding circuit design and operating parameters.